Semiconductor device

ABSTRACT

According to one embodiment, a semiconductor device includes a substrate and an interconnect region on the substrate. The interconnect region includes a first interconnect having a first contact portion whose plane shape is a ring-like plane shape, a second interconnect disposed below the first interconnect, and a contact electrode passing through the ling-like portion of the first contact portion and electrically connecting the first interconnect and the second interconnect.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2010-113533, filed May 17, 2010; theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device.

BACKGROUND

A semiconductor memory as a semiconductor device is mounted on variouselectronic equipment. Recently, resistance change memories such as ReRAM(Resistive RAM) using a variable resistance device as a memory device,PCRAM (Phase Change RAM) using a phase change device as a memory device,and the like have received attention as a next generation non-volatilesemiconductor memory.

These resistance change memories have a feature in that a memory cellarray is of a cross point type and can realize a large memory capacityby a three-dimensional integration and operation at a high speed similarto a DRAM (refer to, for example, Jpn. PCT National Publication No.2005-522045).

In the resistance change memory, a cross point type memory cell arrayincludes cell units. Each of the cell units is formed of a memory deviceand a non-ohmic device. In the cross point type memory cell array, thecell units are disposed two-dimensionally as well as stacked in avertical direction with respect to a substrate surface.

The resistance change memory having the stacked structure includes acontact electrode for connecting an interconnect having a certaininterconnect level and another interconnect having a differentinterconnect level (an upper layer or a lower layer) (refer to, forexample, Jpn. Pat. Appln. KOKAI Publication No. 2009-130140 reference).In the cross point type memory cell array, a contact portion connectedto the contact electrode is disposed to a part of the interconnect.

In a semiconductor device such as the resistance change memory, when aconnecting state of a contact electrode and an interconnect (contactportion) is deteriorated, a contact resistance of the contact electrodeand the interconnect is increased, and electric characteristics of eachinterconnect are dispersed. Further, when an area for disposing thecontact electrode and the contact portion is simply reduced here, thedispersion of the electric characteristics is increased.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is view showing a resistance change memory of an example of asemiconductor device of an embodiment of the invention;

FIG. 2 is a view showing a configuration example of a cross point typememory cell array;

FIG. 3A is view showing a configuration example of a cell unit of thememory cell array of FIG. 2;

FIG. 3B is view showing an example of the cell unit;

FIG. 4 is view showing a connection relation between a memory device anda rectifier device;

FIG. 5A is view showing a layout of first and second control circuits;

FIG. 5B is view showing a layout of first and second control circuits;

FIG. 6 is view showing a layout of first and second control circuits;

FIG. 7 is view showing a layout in the vicinity of the memory cellarray;

FIG. 8 is a plan view showing a basic example of an interconnect and acontact of a semiconductor device of the embodiment;

FIG. 9 is a sectional view showing the basic example of the interconnectand the contact of the semiconductor device of the embodiment;

FIG. 10 is view describing a configuration of the interconnect and thecontact of the semiconductor device of the embodiment;

FIG. 11 is view showing a structure example of an interconnect and acontact of a resistance change memory;

FIG. 12 is view showing a structure example of an interconnect and acontact of a resistance change memory;

FIG. 13 is view showing a structure example of an interconnect and acontact of a resistance change memory;

FIG. 14A is view showing a process of a method of manufacturing theresistance change memory;

FIG. 14B is view showing a process of a method of manufacturing theresistance change memory;

FIG. 14C is view showing a process of a method of manufacturing theresistance change memory;

FIG. 15A is view showing a process of a method of manufacturing theresistance change memory;

FIG. 15B is view showing a process of a method of manufacturing theresistance change memory;

FIG. 15C is view showing a process of a method of manufacturing theresistance change memory;

FIG. 16A is view showing a process of a method of manufacturing theresistance change memory;

FIG. 16B is view showing a process of a method of manufacturing theresistance change memory;

FIG. 17 is view showing a process of a method of manufacturing theresistance change memory;

FIG. 18A is view showing a process of a method of manufacturing theresistance change memory;

FIG. 18B is view showing a process of a method of manufacturing theresistance change memory;

FIG. 19A is view showing a process of a method of manufacturing theresistance change memory;

FIG. 19B is view showing a process of a method of manufacturing theresistance change memory;

FIG. 20 is a view describing a modification of the semiconductor deviceof the embodiment;

FIG. 21A is a view describing a modification of the semiconductor deviceof the embodiment;

FIG. 21B is a view describing a modification of the semiconductor deviceof the embodiment;

FIG. 22A is a view describing a modification of the semiconductor deviceof the embodiment;

FIG. 22B is a view describing a modification of the semiconductor deviceof the embodiment; and

FIG. 23 is a view describing a modification of the semiconductor deviceof the embodiment.

DETAILED DESCRIPTION

A semiconductor device according to an embodiment will be describedbelow in detail referring to the drawings. In the following description,the components having the same functions and the same configurations aredenoted by the same reference numerals and will be described induplication when necessary.

In general, according to one embodiment, a semiconductor device includesa substrate and an interconnect region on the substrate. Theinterconnect region includes a first interconnect having a first contactportion whose plane shape is a ring-like plane shape, a secondinterconnect disposed below the first interconnect, and a contactelectrode passing through the ling-like portion of the first contactportion and electrically connecting the first interconnect and thesecond interconnect.

A subject of the embodiment is a resistance change memory as asemiconductor device using, for example, a variable resistance device ora phase change device as a memory device.

Embodiment (1) Basic Example

A semiconductor device according to an embodiment will be describedusing FIGS. 1, 2, 3, 4, 5, 6, 7, 8, 9, and 10. In the embodiment, aresistance change memory will be described as an example of thesemiconductor device.

FIG. 1 shows a main portion of the resistance change memory.

The resistance change memory (for example, chip) 1 includes a crosspoint type memory cell array 2.

A first control circuit 3 is disposed to an end of the cross point typememory cell array 2 in a first direction, and a second control circuit 4is disposed to one end in a second direction intersecting the firstdirection.

The first control circuit 3 selects a row of the cross point type memorycell array 2 based on, for example, a row address signal. Further, thesecond control circuit 4 selects a column of the cross point type memorycell array 2 based on, for example, a column address signal.

The first and second control circuits 3, 4 control write, erase, andread of data to a memory device in the memory cell array 2.

In the resistance change memory 1 of the embodiment, for example, thewrite is referred to as a set and the erase is referred to as a reset.It is sufficient that a resistance value of a set state is differentfrom a resistance value of a reset state, and it is not importantwhether the resistance value of the set state is higher or lower thanthe resistance value of the reset state.

Further, a multi-level resistance change memory, in which one memorydevice stores multi-level data, can be also realized by selectivelywriting one level of levels of resistance values which can be set to thememory device in a set operation.

A controller 5 supplies a control signal and data to the resistancechange memory 1. The control signal is input to a command interfacecircuit 6, and the data is input to a data input/output buffer 7. Thecontroller 5 may be disposed in the chip 1 or may be disposed in a chip(host device) different from the chip 1.

The command interface circuit 6 determines whether or not data from thecontroller 5 is command data based on the control signal. When the datais the command data, the command interface circuit 6 transfers the datafrom the data input/output buffer 7 to a state machine 8.

The state machine 8 manages an operation of the resistance change memory1 based on the command data. For example, the state machine 8 manages aset/reset operation and a read operation based on the command data fromthe controller 5. It is also possible for the controller 5 to receivestatus information managed by the state machine 8 and to determine aresult of operation in the resistance change memory 1.

In the set/reset operation and the read operation, the controller 5supplies an address signal to the resistance change memory 1. Theaddress signal is input to the first and second control circuits 3, 4via an address buffer 9.

A potential supply circuit 10 outputs a voltage pulse or a current pulsenecessary for, for example, the set/reset operation and the readoperation at a predetermined timing based on a command from the statemachine 8. The potential supply circuit 10 includes, for example, apulse generator 10A and controls the voltage value/current value and thepulse width of a voltage pulse/current pulse output in response to anoperation shown by the command data and the control signal.

Hereinafter, circuits other than the cross point type memory cell array2, which constitutes the resistance change memory (chip), are calledperipheral circuits.

FIG. 2 is a bird's eye view showing a structure of the cross point typememory cell array.

The cross point type memory cell array 2 is disposed on a substrate 11.The substrate 11 is a semiconductor substrate (for example, a siliconsubstrate) or an interlayer insulation film on the semiconductorsubstrate. Note that when the substrate 11 is the interlayer insulationfilm, a circuit using a field effect transistor and the like may beformed on the surface of the semiconductor substrate under the crosspoint type memory cell array 2 as a peripheral circuit of the resistancechange memory.

The cross point type memory cell array 2 has a stack structure of, forexample, memory cell arrays (also called memory cell layers).

FIG. 2 shows, as an example, a case in which the cross point type memorycell array 2 has four memory cell arrays, M1, M2, M3 and M4, stacked ina third direction (direction vertical to a main plane of the substrate11). It is sufficient that at least two memory cell arrays are stacked.Note that the cross point type memory cell array 2 may have one memorycell array. Further, an insulation film may be disposed between twostacked memory cell arrays and the two memory cell arrays may beelectrically separated by the insulation film.

As shown in FIG. 2, when the memory cell arrays M1, M2, M3 and M4 arestacked, the address signal includes, for example, a memory cell arrayselection signal, a row address signal, and a column address signal. Thefirst and second control circuits 3, 4 select one of the stacked memorycell arrays based on, for example, the memory cell array selectionsignal. The first and second control circuits 3, 4 can write, erase, andread data to one of the stacked memory cell arrays or can also write,erase, and read data to at least two or all of the stacked memory cellarrays at the same time.

The memory cell array M1 includes cell units CU1 disposed in first andsecond directions in an array state. Likewise, the memory cell array M2includes cell units CU2 disposed in the array state, the memory cellarray M3 includes cell units CU3 disposed in the array state, and thememory cell array M4 includes cell units CU4 disposed in the arraystate.

Further, control lines L1(j−1), L1(j), L1(j+1), control lines L2(i−1),L2(i), L2(i+1), control lines L3(j−1), L3(j), L3(j+1), control linesL4(i−1), L4(i), L4(i+1), and control lines L5(j−1), L5(j), L5(j+1) aresequentially disposed on the substrate 11 from the substrate 11 side.

Odd numbers of interconnects from the substrate 11 side, that is, thecontrol lines L1(j−1), L1(j), L1(j+1), the control lines L3(j−1), L3(j),L3(j+1), and the control lines L5(j−1), L5(j), L5(j+1) extend in thesecond direction.

Even numbers of interconnects from the semiconductor substrate 11 side,that is, the control lines L2 (i−1), L2(i), L2(i+1), and the controllines L4(i−1), L4(i), L4(i+1) extend in the first direction intersectingthe second direction.

The control lines are used as word lines or bit lines.

The first memory cell array M1 of a lowermost layer is disposed betweenthe first control lines L1(j−1), L1(j), L1(j+1) and the second controlline L2(i−1), L2(i), L2(i+1). In the set/reset operation and the readoperation of the memory cell array M1, one control lines of the controllines L1(j−1), L1(j), L1(j+1) or the control lines L2(i−1), L2(i),L2(i+1) are used as the word lines, and the other control lines are usedas the bit lines.

The memory cell array M2 is disposed between the second control linesL2(i−1), L2(i), L2(i+1) and the third control line L3 (j−1), L3(j),L3(j+1). In the set/reset operation and the read operation of the memorycell array M2, one control lines of the control lines L2(i−1), L2(i),L2(i+1) or the control lines L3(j−1), L3(j), L3(j+1) are used as theword lines, and the other control lines are used as the bit lines.

The memory cell array M3 is disposed between the third control linesL3(j−1), L3(j), L3(j+1) and the fourth control lines L4(i−1), L4(i),L4(i+1). In the set/reset operation and the read operation of the memorycell array M3, one control lines of the control lines L3(j−1), L3(j),L3(j+1) or the control lines L4(i−1), L4(i), L4(i+1) are used as theword lines, and the other control lines are used as the bit lines.

The memory cell array M4 is disposed between the fourth control linesL4(i−1), L4(i), L4(i+1) and the fifth control lines L5(j−1), L5(j),L5(j+1). In the set/reset operation and the read operation of the memorycell array M4, one control lines of the control lines L4(i−1), L4(i),L4(i+1) or the control lines L5(j−1), L5(j), L5(j+1) are used as theword lines, and the other control lines are used as the bit lines.

The cell units CU1 are disposed to the portions where the control linesL1(j−1), L1(j), L1(j+1) intersect the control lines L2(i−1), L2(i),L2(i+1). Likewise, the cell units CU2, CU3, CU4 are disposedrespectively to the portions where the control lines L2(i−1), L2(i),L2(i+1) intersect the control lines L3(j−1), L3(j), L3(j+1), theportions where the control lines L3(j−1), L3(j), L3(j+1) intersect thecontrol lines L4(i−1), L4(i), L4(i+1), and the portions where thecontrol lines L4(i−1), L4(i), L4(i+1) intersect the control linesL5(j−1), L5(j), L5(j+1). More specifically, in the cross point typememory cell array 2, the cell units are disposed to the portions wherethe control lines, which are continuously stacked in the thirddirection, intersect.

Note that, when the stacked memory cell arrays are separated torespective layers by insulation films, the control lines extending inthe first and second directions are not shared by the two stacked memorycell arrays, and control lines as the word lines and as the bit linesare disposed to the memory cell arrays of the respective layers.

FIG. 3A shows an example of a structure of interconnects and cell unitsin the cross point type memory cell array. FIG. 3B shows an example of amore specific structure of one cell unit.

FIG. 3A shows the cell units CU1, CU2 in the two memory cell arrays M1,M2 in FIG. 2. The configuration of the cell units in the two memory cellarrays M3, M4 in FIG. 2 are the same as the configuration of the cellunits in the two memory cell arrays M1, M2 in FIG. 2.

The stacked cell units CU1, CU2 share the one control line L2(i).

One end of a current path of the cell unit CU1 is connected to thecontrol line L1(j), and the other end of the current path of the cellunit CU1 is connected to the control line L2(i). One end of a currentpath of the cell unit CU2 is connected to the control line L2(i), andthe other end of the current path of the cell unit CU2 is connected tothe control line L3(j).

Each of the cell units CU1, CU2 includes a memory device and a non-ohmicdevice. The memory device is connected in series to the non-ohmicdevice. For example, a rectifier device is used for the non-ohmicdevice.

Various patterns exist as a connection relation between the memorydevice and the rectifier device as the non-ohmic device. However, it isnecessary that all the cell units in one memory cell array have the sameconnection relation between the memory device and the rectifier device.

FIG. 4 shows the connection relation between the memory device and therectifier device.

As to the connection relation between the memory device and therectifier device in one cell unit, there exist two different ways of apositional relation between the memory device and the rectifier deviceand two different ways of the direction of the rectifier, that is, thereexist four different ways of the connection relation in total.Accordingly, as to the cell units in the two memory cell arrays, thereexist 16 different ways (four different ways×four different ways) ofpatterns of the connection relation between the memory device and therectifier device. In FIG. 4, “a” to “p” show the 16 different ways ofthe connection relation. The embodiment can be applied to all the 16different ways of the connection relation.

FIG. 3B shows a structure example of the cell unit CU1 shown in “a” ofFIG. 4.

In the cell unit CU1 of the embodiment of FIG. 3B, a memory device 20 isstacked on a non-ohmic device 30. A stacked body including the memorydevice 20 and the non-ohmic device 30 is sandwiched between the twocontrol lines L2(i), L3(j) as one cell unit CU. However, the structureof the cell unit CU shown in FIG. 3A is an example, and the non-ohmicdevice 30 may be stacked on the memory device 20 in response to aconnection relation between the cell unit shown in FIG. 4.

The memory device 20 is a variable resistance device or a phase changedevice. Here, the variable resistance device is a device including amaterial whose resistance value is changed by an application of energysuch as a voltage, a current, and heat. Further, the phase change deviceis a device including a material in which a crystal phase of the deviceis changed by the energy applied thereto and a physical property(impedance) such as a resistance value and a capacitance is changed bythe phase change.

Such phase change (phase transition) includes the ones shown below.

Metal-semiconductor transition, metal-insulator transition, metal-metaltransition, insulator-insulator transition, insulator-semiconductortransition, insulator-metal transition, semiconductor-semiconductortransition, semiconductor-metal transition, semiconductor-insulatortransition

Phase change (metal-superconductor transition and the like) in quantumstate

Paramagnetic-ferromagnetic transition, anti ferromagnetic-ferromagnetictransition, ferromagnetic-ferromagnetic transition,ferrimagnetic-ferromagnetic transition, and transitions composed ofthese transitions

Paraelectric-ferroelectric transition, paraelectric-pyroelectrictransition, paraelectric-piezoelectric transition,ferroelectric-ferroelectric transition, anti ferroelectric-ferroelectrictransition, and transitions composed of these transitions

Transitions composed of a combination of these transitions

For example, transition from metal, insulator, semiconductor,ferroelectric, paraelectric, pyroelectric, piezoelectric, ferromagnetic,ferrimagnetic, spiral magnetic body, paramagnetic, or antiferromagneticto a ferroelectric ferromagnetic material and transition opposite to theabove transition.

According to the definition, the variable resistance device includes thephase change device.

In the embodiment, the variable resistance device is mainly composed ofmetal oxides (for example, binary or ternary metal oxides and the like),metal compounds, chalcogenide materials (for example, Ge—Sb—Te,In—Sb—Te, and the like), organic substances, carbon, carbon nanotubes,and the like.

Note that the resistance value of a magneto-resistive effect elementused for an MRAM (Magnetoresistive RAM) is also changed by changing arelative direction of magnetization of two magnetic layers of thedevice. In the embodiment, a magneto-resistive effect element, forexample, MTJ (Magnetic Tunnel Junction) device is also included in thevariable resistance device.

An operation called a bipolar operation and an operation called aunipolar operation exist as a method of changing the resistance value ofthe memory device 20.

The bipolar operation reversibly changes the resistance value of thememory device 20 between at least a first value (first level) and asecond value (second level) by changing the polarity of a voltageapplied to the memory device 20. The bipolar operation is employed to amemory in which it is necessary to flow a current for a memory device ina dual direction in a write operation as in, for example, a spintransfer type MRAM and the like.

The unipolar operation reversibly changes a resistance value of a memorydevice between at least a first value and a second value by controllingthe magnitude of a voltage and/or the application time (pulse width) ofthe voltage without changing the polarity of the voltage applied to thememory device.

The memory device 20 includes electrode layers 25, 26 at one end and theother end in the third direction (stacked direction). The electrodelayer 25 is disposed at a bottom portion of the memory device 20, andthe electrode layer 26 is disposed at an upper portion of the memorydevice 20. The electrode layers 25, 26 are used as, for example,electrodes of the memory device. For example, a metal film, a metalcompound film, a conductive semiconductor film, or a stacked film ofsuch is used as the electrode layers 25, 26.

In the embodiment, a portion sandwiched between the two electrode layers25, 26 is referred to as a resistance change film 21. The resistancechange film 21 is a film formed of a material whose resistance value orcrystal phase is changed by energy such as a voltage, a current, andheat. The resistance change film 21 includes a material having aproperty such that a resistance value or a crystal phase of the filmitself changes due to the energy applied thereto.

In contrast, the resistance change film 21 may be composed of a materialhaving a property such that the resistance value (or the crystal phase)is changed by changing the interface characteristics between theresistance change film 21 and the electrode layers 25, 26 by the energyapplied to the material. In the case, the property for changing theresistance value of the memory device 20 is stably obtained by acombination of a material used for the resistance change film 21 and amaterial used for the electrode layers 25, 26.

The electrode layers 25, 26 may have a function as diffusion preventionlayers. The diffusion prevention layers prevent impurities caused by thelower device 30 and the control lines from dispersing to the memorydevice 20 or prevent impurities caused by the memory device 20 fromdispersing to the lower device and the control lines.

Further, the electrode layers 25, 26 may have a function as adhesionlayers for preventing the memory device 20 from exfoliating the lowerdevice 30 and the control lines.

The non-ohmic device 30 is a device whose input/output characteristics(voltage-current characteristics) do not have linearity, that is, adevice whose input/output characteristics have non-ohmiccharacteristics.

The non-ohmic device 30 includes conductive layers 35, 36 at one end andthe other end in the third direction (stacked direction). The conductivelayer 35 is disposed at a bottom portion of the non-ohmic device 30, andthe conductive layer 36 is disposed at an upper portion of the non-ohmicdevice 30.

The conductive layers 35, 36 are used as electrodes of, for example, thenon-ohmic device. The conductive layers 35, 36 include any one ofsilicide, metal, a metal compound, a conductive semiconductor, and thelike. Further, the conductive layers 35, 36 may be stacked bodies ofthese materials. Hereinafter, the conductive layers 35, 36 for whichsilicide is used will be particularly referred to as silicide layers 35,36.

FIG. 3B exemplifies a PIN diode as the non-ohmic device. The PIN diodeis a diode having an intrinsic semiconductor layer between a P-typesemiconductor layer (anode layer) and an N-type semiconductor layer(cathode layer). In the structure shown in FIG. 3, a layer 32 sandwichedbetween two layer 31, 33 is the intrinsic semiconductor layer, one ofthe two layers 31, 33, that is, the layer 33 is the P-type semiconductorlayer, and the other remaining layer 31 is the N-type semiconductorlayer. Note that the intrinsic semiconductor layer includes not only acase in which it does not contain N-type or P-type impurities at all butalso a case in which it has an impurity concentration lower than theimpurity concentrations of the N-type and P-type semiconductor layers.

The non-ohmic device is not limited to the PIN diode shown in FIG. 3B,and the PN diode, a MIS diode, a SIS structure, a MIM structure, and thelike may be appropriately used in response to an operation required bythe cell unit.

The PN diode is a diode in which a P-type semiconductor layer (anodelayer) and an N-type semiconductor layer (cathode layer) form a PNjunction. The MIS (Metal-Insulator-Semiconductor) diode is a diodehaving an insulation layer between a metal layer and a semiconductorlayer. The MIM (Metal-Insulator-Metal) structure and the SIS(Semiconductor-Insulator-Semiconductor) structure are devices having astructure in which an insulation layer is sandwiched between two layerscomposed of a metal layer or a semiconductor layer.

In the resistance change memory driven by the unipolar operation, arectifier device such as a diode is mainly used as the non-ohmic device30. In the resistance change memory driven by the bipolar operation, theMIM structure and the SIS structure are mainly used as the non-ohmicdevice 30.

In the embodiment, the resistance change memory using the unipolaroperation will be described. However, it is needless to say that theresistance change memory of the embodiment may be the memory using thebipolar operation.

FIGS. 5A and 5B show a first example of a layout of first and secondcontrol circuits.

A memory cell array Ms of FIG. 5A corresponds to any one layer of thememory cell arrays M1, M2, M3 and M4 shown in FIG. 2. As shown in FIG.5A, the memory cell array Ms includes cell units CUs disposed in anarray state. One end of each of the cell units CUs is connected tocontrol lines Ls(j−1), Ls(j), Ls(j+1), and the other end of each of thecell units CUs is connected to control lines Ls+1(i−1), Ls+1(i),Ls+1(i+1).

As shown in FIG. 5B, a memory cell array Ms+1 includes cell units CUs+1disposed in the array state. One end of each of the cell units CUs+1 isconnected to control lines Ls+1(i−1), Ls+1(i), Ls+1(i+1), and the otherend of each of the cell units is connected to control lines Ls+2(j−1),Ls+2(j), Ls+2(j+1).

However, in FIG. 5A and FIG. 5B, “s” is set to 1, 3, 5, 7, . . . .

A first control circuit 3 is connected to one end of each of the controllines Ls+1(i−1), Ls+1(i), Ls+1(i+1) in a first direction via switchdevices SW1. The switch devices SW1 are controlled by, for example,control signals φs+1(i−1), φs+1(i), φs+1(i+1). The switch devices SW1are formed of, for example, an N channel type field effect transistor(FET).

A second control circuit 4 is connected to one end of each of thecontrol lines Ls(j−1), Ls(j), Ls(j+1) in a second direction via switchdevices SW2. The switch devices SW2 are controlled by, for example,control signals φs(j−1), φs(j), φs(j+1). The switch devices SW2 areformed of, for example, an N channel type FET.

The second control circuit 4 is connected to one end of each of controllines Ls+2(j−1), Ls+2(j), Ls+2(j+1) in the second direction via switchdevices SW2′. The switch devices SW2′ are controlled by, for example,control signals φs+2(j−1), φs+2(j), φs+2(j+1). The switch devices SW2′are formed of, for example, an N channel type FET.

FIG. 6 shows a second example of the layout of the first and secondcontrol circuits. Note that, in FIG. 6, since the internal configurationof memory cell arrays Ms, Ms+1, Ms+2, Ms+3 is substantially the same asthe memory cell arrays shown in FIG. 5A or FIG. 5B, an illustration ofthe internal configuration of the memory cell arrays will not berepeated in FIG. 6.

The layout of the second example is different from the layout of thefirst example in that the first control circuits 3 are disposed at bothends of the memory cell arrays Ms, Ms+1, Ms+2, Ms+3 in the firstdirection, respectively, and the second control circuits 4 are disposedat both ends of the memory cell array Ms, Ms+1, Ms+2, Ms+3 in the seconddirection, respectively. However, “s” of FIG. 6 is set to 1, 5, 9, 13, .. . .

The first control circuits 3 are connected to both ends of the controllines Ls+1(i−1), Ls+1(i), Ls+1(i+1) in the first direction via theswitch devices SW1 respectively. The switch devices SW1 are controlledby, for example, control signals φs+1(i−1), φs+1(i), φs+1(i+1),φs+3(i−1), φs+3(i), φs+3(i+1). The switch devices SW1 are formed of, forexample, an N channel type FET.

The second control circuits 4 are connected to both ends of the controllines Ls(j−1), Ls(j), Ls(j+1) in the second direction, respectively viathe switch devices SW2. The switch devices SW2 are controlled by, forexample, control signals φs(j−1), φs(j), φs(j+1), φs+2(j−1), φs+2(j),φs+2(j+1). The switch devices SW2 are formed of, for example, an Nchannel type FET.

In the resistance change memory using the unipolar operation, thepotential levels of the two control lines to which a selected cell unit,which is subjected to the set/reset operation, are controlled so that aforward bias is applied to the non-ohmic device (for example, the PINdiode). In contrast, the potential levels of two control lines, to whichthe remaining cell units (non-selected cell units) excluding theselected cell unit are connected, are controlled so that a reverse biasis applied to the non-ohmic devices or so that the potential differencebetween the terminals of the non-ohmic devices becomes 0V.

In the set operation, a voltage of, for example, 3V to 6V is applied tothe memory devices in the selected cell unit for a period (pulse width)of about 10 ns to 100 ns. A current value of a set current applied tothe memory devices (in a high resistance state) is, for example, about10 nA, and the current density of the set current is set to a valuewithin a range of 1×10⁵ to 1×10⁷ A/cm². As a result, the resistancestate of the memory devices in the selected cell unit changes from thehigh resistance state to a low resistance state.

In the reset operation, a voltage of about 0.5V to 3V is applied to thememory devices in the selected cell unit for a period (pulse width) of200 ns to 1 μs. The current value of a reset current applied to thememory devices (in the low resistance state) is about 1 μA to 100 μA,and the current density of the set current is set to a value within arange of 1×10³ to 1×10⁶ A/cm². As a result, the resistance state of thememory devices in the selected cell unit changes from the low resistancestate to the high resistance state.

Note that the current value of the set current is different from thecurrent value of the reset current. Further, when the set/resetoperation of the memory devices depends on the pulse widths of thecurrent and the voltage, the pulse width of the set current is differentfrom the pulse width of the reset current. The voltage value and theperiod (pulse width) for changing the resistance value of the memorydevices in the cell unit depend on a material of the memory devices.

In the read operation of the resistance change memory, the potentiallevel of a selected control line is controlled so that a forward bias isapplied to the non-ohmic devices in the selected cell unit likewise inthe set/reset operation. It is necessary that the current value of aread current I-read is sufficiently smaller than the current value of aset current I-set and the current value of a reset current I-reset sothat the resistance value of the memory devices does not change in theread operation. Further, when the change of the resistance value of thememory devices depends on the pulse width of the current, the pulsewidth of the read current is set to a pulse width by which theresistance value of the memory devices does not change.

In the resistance change memory shown in FIGS. 5A, 5B, and 6, an area inwhich interconnects are wired is formed in the chip 1 to connect thecontrol lines of the cross point type memory cell array 2 to theperipheral circuits 3, 4 in the chip 1. The interconnect wiring area isreferred to as an interconnect region in the embodiment.

For example, as shown in FIG. 7, an interconnect region 15 is formed onthe substrate (for example, the interlayer insulation film) 11 to beadjacent to a region (hereinafter, called a memory cell array region) 12in which the cross point type memory cell array 2 is disposed. Then, thecontrol circuits 3, 4 and the other circuits 6, 7, 8, 9 and 10 aredisposed as peripheral circuits on the surface of the semiconductorsubstrate (active region) under the memory cell array region 12 and theinterconnect region 15.

Note that, in FIG. 7, the interconnect region 15 is disposed so as tosurround the memory cell array region 12. However, the interconnectregion 15 is not limited to this configuration and may be disposedadjacent only to an end of the memory cell array region 12 in the firstdirection (or the second direction), or the interconnect regions 15 maybe disposed adjacent to one end and the other end of the memory cellarray region 12 in the first direction (or the second direction).

The control lines included in the cross point type memory cell array aredrawn out from inside of the memory cell array region 12 to theinterconnect region 15. To simplify the illustration, FIG. 7 shows thecontrol lines L1 (j) extending in the second direction and the controllines L2(i) extending in the first direction of the control lines.

A conversion of the line width of the control lines L1(j), L2 (i), aconversion of the interconnect pitch between the control lines(interconnects), or a connection between interconnects at differentinterconnect levels are executed in the interconnect region 15.

Interconnects 40 in the interconnect region 15 continuously extend from,for example, the memory cell array region 12. However, the interconnects40 in the interconnect region 15 are individually disposed in theinterconnect region 15, and some of the interconnects 40 are connectedto the control lines L1(i), L2(j), which are drawn out from the memorycell array region 12 to the interconnect region 15, in the interconnectregion 15.

Contact electrodes (ref. 60 in FIG. 8) are disposed in the interconnectregion 15. The contact electrodes electrically connect at least twointerconnects 40 having a different interconnect level. The contactelectrodes are in contact with contact portions 41 disposed at parts ofthe interconnects 40. In the embodiment, the interconnect level meansthe height of the interconnects (a position in the third direction)based on a substrate surface as a reference.

The semiconductor device (here, the resistance change memory) of theembodiment includes the control lines L1(j), L2(i) and/or theinterconnects 40 having the ring-like contact portions 41. Hereinafter,a case, in which the interconnects 40 (control lines L1(j), L2(i)) havethe ring-like contact portions 41 in the interconnect region 15, will bedescribed. However, it is needless to say that the embodiment includes acase in which the ring-like contact portions 41 are disposed at thecontrol lines L1(j), L2(i) and the interconnects 40 in the memory cellarray region 12.

An interconnect having the ring-like contact portion 41 will bedescribed using FIGS. 8, 9, and 10. FIG. 8 is a plan view in which aportion, in which a contact portion 41 of an interconnect 40 is formed,is extracted. FIG. 9 is a sectional view along an IX-IX line of FIG. 8.FIG. 10 is a schematic view describing a connection relation between aninterconnect to which the ring-like contact portion 41 is disposed and acontact electrode.

As shown in FIGS. 8 to 10, two interconnects, 40, 50, are disposed inthe interconnect region 15.

The interconnect 40, the interconnect 50, an interlayer insulation film81, an interlayer insulation film 82, and an interlayer insulation film83 are disposed on the substrate 11 via an interlayer insulation film17. The interconnect 40 is disposed in the interlayer insulation film82, and the interconnect 50 is disposed in the interlayer insulationfilm 81 below the interconnect 40. The interlayer insulation film 83 isdisposed above the interlayer insulation film 82.

The interconnect 40 and the interconnect 50 are disposed at differentinterconnect levels, respectively, so that the interconnect 40 isoverlapped above the interconnect 50 in the stacked direction (thirddirection) of the interlayer insulation films 81, 82, 83.

In FIGS. 8 to 10, the interconnect 40 extends in the first direction,and the interconnect 50 extends in the second direction intersecting thefirst direction. However, as long as the two interconnects 40, 50 aredisposed in a layout in which they are overlapped vertically (the thirddirection), the two interconnects 40, 50 may extend in other directionsor in the same direction, respectively.

The contact portion 41 is disposed at a portion of the interconnect 40.The portion (location) of the interconnect 40 where the contact portion41 is disposed may be an end portion of the interconnect 40 in adirection in which the interconnect extends or may be a portion otherthan the end portion of the interconnect.

The contact portion 41 projects in a direction (the second direction inFIG. 8) intersecting the extending direction (the first direction inFIG. 8) of the interconnect 40 in a direction (horizontal direction)parallel to the surface of the substrate 11. Note that the contactportion 41 of the interconnect 40 includes not only a portion projectingin the direction intersecting the extending direction of theinterconnect 40 but also a portion extending in the extending directionof the interconnect 40.

The contact portion 41 is formed above the interconnect 50 at aninterconnect level below the interconnect 40. The contact portion 41 isdisposed at a position where it overlaps the lower interconnect 50vertically.

The contact portion 41 of the embodiment has a ring-like plane shapewhen viewed from a vertical direction (third direction) to the surfaceof the substrate 11. In the embodiment, the ring shape is a squareannular shape or a circular annular shape, and the portion excluding anouter peripheral portion of the contact portion is configured as athrough hole.

The ring-like contact portion 41 having the ring-like plane includes anopening portion (through hole) 49 formed thereto. The opening portion 49is positioned above the interconnect 50. In the embodiment, the portionexcluding the opening portion 49 of the contact portion 41 is referredto as a ring portion 48.

In FIG. 8, although the ring portion 48 and the opening portion 49 ofthe contact portion 41 have a square plane shape, they are not limitedto the square plane shape.

A contact electrode 60 is buried in a contact hole formed in theinterlayer insulation films 82, 81 across them. The contact electrode 60is in contact with the two interconnects 40, 50 having differentinterconnect levels.

The contact electrode 60 is in contact with the ring portion 48 formedin the contact portion 41 of the interconnect 40. The contact electrode60 is in contact with the upper surface of the interconnect 50 below theinterconnect 40 via (passing through) the opening portion 49 formed inthe contact portion 41 of the interconnect 40.

In the direction horizontal to the substrate surface, the size of aportion 61 of the contact electrode 60, which is in contact with theupper surface of the contact portion 41, is set larger than the size ofa portion 62 under the portion 61 of the contact electrode 60. That is,the contact electrode 60 has a sectional shape formed convex in adownward direction.

Hereinafter, in the contact electrode 60, the portion 61 on the uppersurface of the contact portion 41 is referred to as an upper electrodeportion 61, and the portion 62 under the upper portion 61 is referred toas a lower electrode portion 62.

The size of the lower electrode portion 62 in the direction horizontalto the substrate surface is set equal to or smaller than the size of theopening portion 49 of the contact portion 41.

Note that although the contact electrode 60 includes the two electrodeportions 61, 62, it is composed of one continuous conductor. Further,although the contact electrode 60 has the square plane shape in FIG. 8,it may have a plane shape including a curved line such as a circularshape and an oval shape.

The contact areas between the respective interconnects 40, 50 and thecontact electrode 60 will be described using FIG. 10. In FIG. 10, anillustration of the interlayer insulation films that cover theinterconnects 40, 50 and the contact electrode 60 will not be repeated.The interconnect 50 is referred to as an interconnect 50 of a lowerlayer (a first interconnect level), and the interconnect 40 is referredto as an interconnect 40 of an upper layer (a second interconnectlevel).

Further, to simplify description, it is assumed that the opening portion49 formed in the contact portion 41 has the square plane shape.Likewise, an upper surface and a bottom surface of the contact electrode60 have a square shape. However, as described above, the plane shape ofthe contact portion 41, the opening portion 49, and the contactelectrode 60 is not limited to the square shape, and a shape includingthe curved line such as the circular shape and the oval shape and asquare shape without corners, or with rounded corners also can beapplied to the embodiment.

As described in FIGS. 8 and 9, the interconnect 40 of the upper layerincludes the ring-like contact portion 41 in FIG. 10. The contactelectrode 60 is in contact with the interconnect 40 of the upper layervia the contact portion 41 as well as in contact with the interconnect50 of the lower layer passing through the ring-like opening portion 49.With such configuration, the contact electrode 60 is electricallyconnected to the interconnect 40 of the upper layer and to theinterconnect 50 of the lower layer.

In FIG. 10, the line width of the ring portion 48 of the contact portion41 is shown by “RW”. The line width RW of the ring portion 48 is setequal to or larger than the line width LW of the interconnect 40.

In FIG. 10, the size of a side of the opening portion 49 formed in thecontact portion 41 along the first direction is shown by “X1”, and thesize of a side of the opening portion 49 along the second direction isshown by “Y1”. The size of the opening portion 49 along the thirddirection is shown by “Z1”. The size Z1 is substantially the same as thefilm thickness of the interconnect 40 and the contact portion 41.

As shown in FIG. 10, the size of the upper surface of the upperelectrode portion 61 of the contact electrode 60 along the firstdirection is shown by “Xce”, and the size of the upper surface of theupper electrode portion 61 along the second direction is shown by “Yce”.The size of the contact electrode 60 from an upper end to the contactportion 48 along the third direction is shown by “Zce”. The sizes Xce,Yce of the upper electrode portion 61 depend on the size of the uppersurface of the contact hole in the interlayer insulation film (notshown) in which the upper electrode portion 61 is buried. Further, thesize Zce of the upper electrode portion 61 of the contact electrode 60depends on the film thickness of the interlayer insulation film in whichthe upper electrode portion 61 is buried.

The contact area (regions Ace1, Ace2 shown by slant lines in FIG. 10) S1between the contact portion (ring portion 48) and the contact electrode60 is the sum of a contact area Ace1 between a bottom surface of theupper electrode portion 61 of the contact electrode 60 and the uppersurface of the contact portion 41 and a contact area Ace2 between thelower electrode portion 62 of the contact electrode 60 and a sidesurface of the opening portion 49 (ring portion 48).

The contact area between the bottom surface of the upper electrodeportion 61 of the contact electrode 60 and the upper surface of thecontact portion 41 corresponds to the value obtained by subtracting thearea (X1×Y1) of the upper surface of the opening portion 49 from thearea (Xa×Ya) of the bottom surface of the contact electrode 60.

The contact area between the lower electrode portion 62 of the contactelectrode 60 and the side surface of the opening portion 49 (ringportion 48) corresponds to the area (Z1×(2×X1+2×Y1)) of the side surfaceof the opening portion 49.

Therefore, the contact area S1 between the contact portion 41 and thecontact electrode 60 is determined by the following Expression 1.

S1=(Xce×Yce−X1×Y1)+Z1×(2×X1+2×Y1)  (Expression 1)

The lower electrode portion 62 of the contact electrode 60 passesthrough the opening portion 49 and comes into contact with theinterconnect 50 below the interconnect 40. The sizes of the uppersurface of the lower electrode portion 62 are substantially the same as,for example, the sizes X1, Y1 of the opening portion 49.

In FIG. 10, the size of a bottom surface of the lower electrode portion62 along the first direction is shown by “X2”, and the size of the lowerelectrode portion 62 along the second direction is shown by “Y2”. In thecase, the contact area S2 between the lower electrode portion 62 of thecontact electrode 60 and the lower interconnect 50 is shown by thefollowing Expression 2.

S2=X2×Y2  (Expression 2)

Note that when the size Zce of the upper electrode portion 61 in thethird direction increases, the sizes Xa, Ya of the bottom surface of theupper electrode portion 61 of the contact electrode 60 tend to becomesmaller than the sizes Xce, Yce of the upper surface of the upperelectrode portion 61. Further, since the contact hole is formed via theopening portion 49, the sizes X1, Y1 of the opening portion 49 becomeapproximately the same as the sizes X2, Y2 of the bottom surface of thelower electrode portion 62. However, the sizes X2, Y2 of the bottomsurface of the lower electrode portion 62 of the contact electrode 60tend to become smaller than the sizes X1, Y1 of the upper surface of thelower electrode portion 62 in response to the magnitude of the size(height) H2 of the lower electrode portion 62 in the third direction;and this relation similarly applies between the sizes Xa, Ya of thebottom surface of the upper electrode portion 61 and the sizes Xce, Yceof the upper surface of the upper electrode portion 61.

Since such tendencies depend on the ratio (aspect ratio) of the size inthe first direction (or the second direction) and the size in the thirddirection, the magnitudes of the contact areas S1, S2 between therespective interconnects 40, 50 and the contact electrode 60 can becontrolled by taking the size of the opening portion 49 of the contactportion 41, the opening size of the contact hole in which the contactelectrode 60 is buried, and the film thickness of the interlayerinsulation films into consideration.

Note that when the size Z1 of the opening portion in the thirddirection, that is, the film thickness Z1 of the interconnect 40 and thecontact portion 41 is sufficiently smaller than the sizes Xce (Xa), Yce(Ya) of the upper electrode portion 61 of the contact electrode 60, theeffective value of the contact area S1 between the contact portion 41and the upper electrode portion 61 becomes the contact area Ace1 betweenthe upper surface of the contact portion 41 (ring portion 48) and thebottom surface of the upper electrode portion 61.

As described above, in the semiconductor device of the embodiment, forexample, in the resistance change memory, the contact electrode 60reaches the lower interconnect 50 via the opening portion 49 of thering-like contact portion 41 formed at the upper interconnect 40. Thatis, the alignment position of the lower electrode portion 62 of thecontact electrode 60 with the lower interconnect 50 can be determined bydetermining the magnitude of the opening portion 49 of the contactportion 41 and the position of the opening portion 49 to the lowerinterconnect 50.

Therefore, in the embodiment, the alignment offset between the contactelectrode 60 and the lower interconnect 50 is less affected by thealignment offset between a mask and an interconnect when the contacthole is formed and affected only by the alignment offset between theinterconnects 40, 50 disposed at the positions where they are overlappedvertically.

Accordingly, in the semiconductor device in which the one contactelectrode 60 is disposed across the interconnects 40, 50 as in theresistance change memory described in the embodiment, a restriction ofalignment between the interconnects 40, 50 and the contact electrode 60,which is caused by a lithography process and an etching process forforming the contact hole in which the contact electrode 60 is buried, isrelaxed.

Accordingly, in the semiconductor device of the embodiment (for example,in the resistance change memory), the margin of an alignment offset ofthe contact electrode 60 connected to the interconnects having differentinterconnect levels can be secured by forming the plane shape of thecontact portion 41 formed at the interconnect in the ring shape, withoutincreasing the sizes of the contact electrode 60 and the contact hole inwhich the contact electrode 60 is buried, and without increasing thesizes of the interconnect 40 and the contact portion 41. As a result,since the sizes of the contact electrode and the contact portion of thesemiconductor device of the embodiment need not be increased, anincrease of the area occupied by the interconnect region can beprevented in the semiconductor device.

Further, in the embodiment, the contact area S1 between the upperinterconnect 40 and the upper electrode portion 61 of the contactelectrode 60 includes the sizes X1, Y1 of the opening portion 49 asparameters as shown in Expression 1.

Since the contact electrode 60 reaches the interconnect 50 passingthrough the opening portion 49, the sizes X2, Y2 of the bottom surfaceof the lower electrode portion 62 of the contact electrode 60 depend onthe sizes X1, Y1 of the opening portion 49.

The contact area S1 between the upper interconnect 40 and the contactelectrode 60 (upper electrode portion 61) can be adjusted by themagnitude of the contact hole in which the contact electrode 60 isburied and the sizes of the ring portion 48 of the contact portion 41.However, the sizes (sizes of the opening portion) of the contact holeare preferably small to prevent the increase of the area occupied by theinterconnect region 15.

When the contact portion 41 is set to a predetermined area, the area(sizes X1, Y1) of the opening portion 49 and the magnitude of the linewidth RW of the ring portion 48 can be adjusted.

When, for example, the line width RW of the ring portion 48 is increasedin the ring-like contact portion 41, the margin of an alignment offsetbetween the contact electrode 60 and the contact portion 41 disposed tothe interconnect 40 can be increased.

Further, when the line width RW of the ring portion 48 is increased,since the size Xce, Yce of the upper electrode portion 61 can beincreased, the contact area between the upper electrode portion 61 ofthe contact electrode 60 and the contact portion 41 can be increased.

Therefore, in the semiconductor device of the embodiment, the margins ofthe sizes of the contact electrode 60 and the margins of the alignmentoffset between the contact portion 41 and the contact electrode 60 canbe increased by adjusting the line width of the ring portion 48 of thecontact portion 41. Further, an increase of the contact resistancebetween the upper interconnect 40 and the contact electrode 60 can besuppressed.

In contrast, since the contact electrode 60 is in contact with the lowerinterconnect 50 via the opening portion (space inside of the ringportion 48) 49, when the area of the opening portion 49 is increased,the contact resistance between the contact electrode 60 and the lowerinterconnect 50 can be reduced.

Therefore, in the semiconductor device of the embodiment, the contactresistance between the interconnect and the contact electrode can bereduced by adjusting the area of the opening portion 49 of the contactportion 41.

Note that when the area of the contact portion 41 is set constant, anincrease of the area (sizes X1, Y1) of the opening portion 49 reducesthe contact area between the upper surface of the ring portion 48 andthe bottom surface of the upper electrode portion 61. However, since thecontact area Ace2 between a side surface of the ring portion 48 in theopening portion 49 and a side surface of the lower electrode portion 62is increased, when the film thickness of the contact portion(interconnect) is increased, even if the opening portion 49 isincreased, the influence of reduction of the contact area between thecontact portion 41 of the upper interconnect 40 and the contactelectrode 60 is reduced.

The contact area S2 between the lower interconnect 50 and the contactelectrode 60 (lower electrode portion 62) can be adjusted (controlled)by the size of the opening portion 49.

That is, the magnitude of the contact area S1 and the magnitude of thecontact area S2 can be made the same magnitude by adjusting the linewidth RW of the ring portion and the sizes X1, Y1 of the opening portion49.

As a result, in the semiconductor device of the embodiment, since themagnitude of the contact resistance generated between the upperinterconnect 40 and the contact electrode 60 and the magnitude of thecontact resistance generated between the lower interconnect 50 and thecontact electrode 60 can be made the same magnitude, a dispersion of thecontact resistances generated at the interconnects can be reduced.

As described above, according to the semiconductor device of theembodiment, the contact electrodes can be stably connected to theinterconnects.

(2) Specific Example

A specific example of the embodiment will be described using FIGS. 11,12, 13, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 17, 18A, 18B, 19A, and19B by exemplifying a resistance change memory such as a ReRAM(Resistive RAM) and PCRAM (Phase Change RAM).

Note that the detailed description of the components and the effectswhich are substantially the same as those described using FIGS. 1 to 10will not be repeated here.

(a) Structure

A structure of the resistance change memory of the specific example ofthe embodiment will be described using FIGS. 11, 12, and 13. Note thatmembers in a front direction and a depth direction in FIGS. 11 and 13are shown by broken lines.

FIG. 11 is a view schematically showing sectional structures of a memorycell array region 12 and an interconnect region 15 described in thespecific example. FIG. 11 shows the sectional structure of the memorycell array region 12 along the first direction.

Although FIG. 11 shows an example in which the interconnect region 15 isdisposed at one end of the memory cell array region 12 in the firstdirection, it is needless to say that the interconnect region 15 may bedisposed at the other end of the memory cell array region 12 in thefirst direction, or the interconnect regions 15 may be disposed at oneend and the other end of the memory cell array region 12 in the seconddirection in response to a layout of interconnects.

As shown in FIG. 11, a cross point type memory cell array 2 is disposedin the memory cell array region 12. Accordingly, the memory cell arrayregion 12 includes stacked cell units CU1, CU2, CU3, CU4 and CU5. Thecell units CU1, CU2, CU3, CU4 and CU5 are stacked on a substrate 11across control lines L1, L2, L3, L4, L5 and L6, respectively. The cellunits CU1, CU2, CU3, CU4 and CU5 and the control lines L1, L2, L3, L4,L5 and L6 are covered by an interlayer insulation film 80.

Interconnects 40A, 40B, 40C and 50 and contact electrodes 60A, 60B, 60Care disposed in the interconnect region 15.

Three interconnects 50, 51, 52 are disposed on an interlayer insulationfilm 17 in the interconnect region 15. The interconnects 50, 51, 52extend in a direction (for example, the second direction) intersectingthe first direction.

In the interconnect region 15, the interconnects 40A, 40B, 40C aredisposed above the interconnects 50, 51, 52. The interconnects 40A, 40B,40C extend in a direction where they intersect the interconnects 50, 51,52.

As shown in FIG. 11, the interconnect 40A is disposed at the sameinterconnect level as the control line L2 and electrically connected tothe control line L2. The interconnect 40B is disposed at the sameinterconnect level as the control line L4 and positioned above theinterconnect 40A. The interconnect 40B is electrically connected to thecontrol line L4. The interconnect 40C is formed at the same interconnectlevel as the control line L6 and positioned above the interconnect 40B.The interconnect 40C is electrically connected to the control line L6.

Note that although FIG. 11 shows the interconnects 40A, 40B, 40C at thesame levels as the control lines L2, L4, L6, it is needless to say thatinterconnects at the same interconnect levels as the control lines L1,L3, L5 are disposed in the interconnect region 15.

The interconnects 40A, 40B, 40C have ring-like contact portions 41A,41B, 41C, respectively.

The contact electrodes 60A, 60B, 60C connect interconnects disposed atdifferent interconnect levels via opening portions of the ring-likecontact portions 41A, 41B, 41C.

The interconnect 40A is connected to the interconnect 50 by the contactelectrode 60A passing through the ring-like contact portion 41A. Theinterconnect 40B is connected to the interconnect 51 by the contactelectrode 60B passing through the ring-like contact portion 41B.

For example, the interconnect 40C is connected to an intermediate layer70 at the same interconnect level as the control line L5 by the contactelectrode 60A passing through the ring-like contact portions 41C. Thecontrol line L5 is positioned at an interconnect level between thecontrol line L4 and the control line L6. Further, the control line L5and the intermediate layer 70 are made of the same material.

The intermediate layer 70 does not have a ring-like contact portion, andthe contact electrode 60C does not pass through the intermediate layer70. The intermediate layer 70 is connected to the interconnect 52 by acontact electrode 69. As a result, the upper interconnect 40C iselectrically connected to the lower interconnect 52 by appropriatelycombining the contact electrode 60C passing through an opening portionin the contact portion 41C, the intermediate layer 70, and the ordinarycontact electrode 69.

FIG. 12 shows a plan view of a region XII of FIG. 11 when viewed fromthe third direction (upper side). FIG. 13 shows cross sections along anA-A′ line and a B-B′ line of FIG. 12. To clarify a difference, FIG. 13shows the cross sections along the A-A′ line and the B-B′ line side byside without showing the interlayer insulation film.

As shown in FIGS. 12 and 13, the interconnect 50 and the interconnect 51are disposed side by side in the first direction when viewed from thethird direction at the same interconnect level (on the substrate 11).

The interconnect 40A and the interconnect 40B are disposed side by sidein planes, where the contact portions 41A, 41B thereof are disposed, inthe second direction when viewed from the third direction. Theinterconnect 40A and the interconnect 40B are disposed at differentinterconnect levels, respectively. Note that the interconnect 40A andthe interconnect 40B are drawn in the interconnect region 15 so thatthey are formed in a predetermined interconnect layout.

The contact portion 41A of the interconnect 40A is disposed at aposition where it is not overlapped vertically on the contact portion41B of the interconnect 40B. The ring-like contact portion 41A ispositioned above the interconnect 50, and the ring-like contact portion41B is positioned above the interconnect 51.

The ring-like contact portion 41A disposed at the interconnect 40Aprojects to the interconnect 40B side with respect to the surface of thesubstrate 11 in a horizontal direction. The ring-like contact portion41B disposed to the interconnect 40B projects to the interconnect 40Aside with respect to the surface of the substrate in the horizontaldirection. The directions in which the contact portions 41A, 41B projectare opposite to each other. An increase of the area of the interconnectregion 15 is suppressed by disposing the contact portions 41A, 41B sothat they alternately project in a different direction in theinterconnects adjacent to each other in the horizontal direction in theplanes with respect to the surface of the substrate 11 when viewed fromthe third direction.

Note that FIGS. 11 to 13 show the example in which the contact portions41A, 41B at the different interconnect levels are disposed so as toalternately project. However, it is needless to say that the same effectcan be also obtained even in a case in which two contact portions at thesame interconnect level alternately project.

As described using FIGS. 8, 9, and 10, the resistance change memoryshown in FIGS. 11, 12, and 13 includes the interconnects 40A, 40B havingthe contact portions 41A, 41B whose plane shape is formed in thering-shape, and the margin of an alignment offset of the contactelectrodes 60A, 60B of the upper interconnects 40A, 40B and of the lowerinterconnects 50, 51 can be secured by controlling the line widths ofthe ring portions 48A, 48B of the contact portions 41A, 41B and thesizes of the opening portions 49A, 49B.

Accordingly, since the resistance change memory of the specific exampleof the embodiment can secure a margin of an alignment offset withoutincreasing the sizes of the contact portions 41A, 41B in theinterconnect region 15 and the sizes of the contact electrodes 60A, 60Band the interconnects 40A, 40B, 50, 51, an increase of the area occupiedby the interconnect region 15 on the surface of the chip (substrate 11)can be suppressed.

The contact area between the contact electrodes 60A, 60B and the upperinterconnects 40A, 40B can be set within a certain predetermined rangeby setting the line widths of the ring portions 48A, 48B of the contactportions 41A, 41B to sizes that account for the alignment offset.Further, the contact area between the contact electrodes 60A, 60B andthe lower interconnects 50, 51 can be adjusted by controlling the sizesof the opening portions 49A, 49B of the contact portions 41A, 41B.

As a result, the contact resistances between the respectiveinterconnects 40A, 40B, 50, 51 and the contact electrodes 60A, 60B inthe specific example of the embodiment of the resistance change memorycan be reduced. Further, as described later, a dispersion of electriccharacteristics of the interconnects 40A, 40B, 50, 51 can be suppressed,resulting from the reduction in a dispersion of the contact resistancesbetween the respective interconnects 40A, 40B, 50, 51 and the contactelectrodes 60A, 60B. Accordingly, the contact electrodes 60A, 60B can beelectrically stably connected to the respective interconnects 40A, 40B,50, 51.

Note that, when the two contact electrode 60A, 61, which are connectedto the interconnects 40A, 40B at the different interconnect levels, areformed by processes executed at the same time, the effect describedabove can be more prominently obtained.

As described above, according to the resistance change memory of thespecific example of the embodiment, occurrence of the alignment offsetof the interconnects and the dispersion of the electric characteristicscan be suppressed.

(b) Manufacturing Method

An example of a manufacturing method of the resistance change memory asa specific example of the embodiment will be described as an example ofthe manufacturing method of the semiconductor device of the embodimentusing FIGS. 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 17, 18A, 18B, 19A,and 19B.

FIG. 14A shows a plane structure of the memory cell array region 12 in aprocess of the manufacturing method of the resistance change memoryaccording to the specific example of the embodiment, and FIG. 14B showsa plane structure of the interconnect region 15. FIG. 14C shows asectional structure along a D-D′ line of FIG. 14A and a sectionalstructure along an E-E′ line of FIG. 14B, respectively. Note that across section along the D-D′ line of FIG. 14A corresponds to a crosssection of the memory cell array region 12 shown in FIG. 2 along thefirst direction.

As shown in FIGS. 14A, 14B, and 14C, a conductive layer is deposited onthe substrate (for example, the interlayer insulation film 17) 11 using,for example, CVD (Chemical Vapor Deposition) and sputtering. Theconductive layer is made into a control line of a lowermost layer in thememory cell array region 12 and an interconnect of a lowermost layer inthe interconnect region 15.

Layers for forming a rectifier device (non-ohmic device) and a memorydevice of a cell unit are sequentially deposited on the conductive layerusing, for example, CVD (Chemical Vapor Deposition) or sputtering. Astacking order of the layers for configuring the cell unit differsaccording to a configuration of the rectifier device and the memorydevice shown in FIG. 4.

When the cell unit has the configuration shown in FIG. 3B, the non-ohmicdevice is, for example, a PIN diode. In the case, three semiconductorlayers are stacked on a lower electrode layer of the non-ohmic deviceformed on an interconnect layer. For example, a silicide layer is formedon an uppermost semiconductor layer (for example, a P-type semiconductorlayer) as upper electrode layers of the PIN diode.

A lower electrode layer, a resistance change film, and an upperelectrode layer of the memory device are sequentially stacked on thesilicide layer.

Further, simultaneously with the deposition of the respective layers onthe memory cell array region 12, layers are deposited on the substrate11 in the interconnect region 15.

The conductive layer and the layers on the substrate 11 are processedusing photolithography, side wall processing, and RIE (Reactive IonEtching), and control lines L1 and stacked bodies 100A extending in thesecond direction are formed. The stacked bodies 100A are formed on thecontrol lines L1. The control lines L1 and the stacked bodies 100A aredisposed side by side in the first direction intersecting the seconddirection.

Simultaneously with the processing of the memory cell array region 12,the interconnect region 15 is processed. For example, layers having thesame configuration as the stacked bodies 100A are removed in theinterconnect region 15, and the interconnects 50 having a predeterminedlayout and shape are formed at the same interconnect level as thecontrol lines L1.

Thereafter, the interlayer insulation film 81 is formed in the memorycell array 2 and in the interconnect region 15 in the substrate 11 by,for example, CVD or coating. With such configuration, the interlayerinsulation film 81 is buried between the cell units adjacent to eachother in the first direction. The interconnect 50 above the substrate 11(interlayer insulation film 17) is covered by the interlayer insulationfilm 81.

After the interlayer insulation film 81 is subjected to a planarprocessing, a conductive layer 59A is formed on the interlayerinsulation film 81 using, for example, sputtering or CVD.

The cell units may be formed by dividing the stacked bodies 100A in thesecond direction using RIE, thereby forming the memory cell array of thelowermost layer. However, to simplify the manufacturing process, it ispreferable to deposit a component of a second memory cell array M2 fromthe substrate side on a conductive layer 59A and to simultaneouslyexecute a processing (etching) in the second direction on a lowermost(first) memory cell array M1 and on a second memory cell array M2without dividing the stacked bodies 100A in the second direction at thisstage.

In the case, layers (stacked bodies) 100B′, which constitute the secondmemory cell array M2 from the substrate side, are formed on theconductive layer 59A. Then, the upper stacked bodies 100B′ and thestacked bodies 100A extending in the first direction are commonlyprocessed in the second direction, respectively by a process describedlater. As a result, the manufacturing process of the resistance changememory having a cross point type memory cell array is simplified and amanufacturing cost of the resistance change memory is reduced ascompared with a case in which each of the memory cell arrays of eachlayer (at each interconnect level) is processed in the first directionand the second direction.

As shown in FIGS. 14A, 14B, and 14C, a mask material used for aprocessing in the second direction is deposited on the stacked bodies100B′ in the memory cell array region 12 and on stacked bodies 101 inthe interconnect region 15. The mask material is processed in apredetermined layout and shape by photolithography and RIE, and coremembers 91 are formed on the stacked bodies 100B′, 101. The core members(mask material) 91 are made of a material which can secure an etchingselect ratio on the conductive layer 59A.

Note that layers (transfer layers), which become substantial masks bybeing transferred with mask patterns, may be disposed between the coremembers 91 and the stacked bodies 100B′.

As shown in FIG. 14A, in the memory cell array region 12, the coremembers 91 have a linear plane pattern extending in the first direction.The linear core members 91 are disposed adjacent to each other in thesecond direction.

The size (line width) W1 of the linear core members 91 in the seconddirection is set, for example, equal to or smaller than a limit ofprocessing executed by photolithography. The adjacent pitch ptc1 of twocore members 91 adjacent in the second direction is, for example, aboutfour times the size of the stacked bodies 100A in the first direction.

In FIG. 14B, core members 91′ in the interconnect region 15 show coremembers 91′ extending in the first direction. However, the core members91′ in the interconnect region 15 are patterned to have a predeterminedlayout and shape in response to a layout of interconnects formed in aprocess, to be described later, different from a layout and shape of thecore members 91′ in the memory cell array region 12.

The core members 91′ in the interconnect region 15 may be members thatcontinue from the memory cell array region 12 to the interconnect region15 or may be members that are separated from the core members 91 of thememory cell array region 12.

The core members 91′ have projecting portions 92 projecting in adirection (for example, the second direction) intersecting the directionin which the core members 91′ extend. The portions of the core members91′ other than the projecting portions 92 are also called main portions.

The projecting portions 92 are formed at the positions where theyoverlap, for example, the lower interconnect 50 vertically. Theprojecting portions 92 are formed at the positions where contactelectrodes are connected to the interconnect 50. The sizes DX1, DX2 ofthe projecting portions 92 in the first and second directions areappropriately set in response to the magnitude of contact portionsdisposed on the interconnects.

The projecting portions 92 disposed on the respective core members 91′are disposed so as to alternately project in two core members 91′adjacent to each other.

The size (line width) W2 of the portions (main portions) of the coremembers 91′ other than the projecting portions 92 in the seconddirection is, for example, equal to or larger than the line width W1 ofthe core members 91 in the memory cell array region 12.

The adjacent pitch ptc2 of the main portions of two core members 91 isset larger than the adjacent pitch ptc1 of the two core members 91′ inthe memory cell array region 12 so that the projecting portion 92 of acore member 91′ is not in contact with another adjacent core member.

FIG. 15A shows a plane structure of the memory cell array region 12 in aprocess of the manufacturing method of the resistance change memory asthe specific example of the embodiment, and FIG. 15B shows a planestructure of the interconnect region 15 in the process of themanufacturing method. FIG. 15C shows a sectional structure along an F-F′line of FIG. 15A and a sectional structure along a G-G′ line of FIG.15B.

As shown in FIGS. 15A, 15B, and 15C, a sidewall masking material isdeposited on the conductive layer 59A in the memory cell array region 12and the interconnect region 15 so as to cover the core members 91, 91′using, for example, CVD or sputtering. The sidewall masking material ismade of a material which can secure an etching selection ratio for thecore members 91, 91′ and the conductive layer 59A.

When anisotropic etching is executed on the sidewall masking material,the mask material remains on side surfaces of the core members 91, 91′and side wall masks 93A, 93A′ are formed in self-alignment so as tosurround the peripheries of the core members 91, 91′. Just after theside wall masks 93A, 93A′ are formed, they have a closed-loop like planeshape around the peripheries of the core members 91, 91′. Loopedportions of the side wall masks 93A, 93A′ are cut off at the ends of thecore members 91, 91′ in the extending direction thereof, and the sidewall masks 93A, 93A′ are formed in independent patterns, respectively.

As shown in FIG. 15A and FIG. 15C, the side wall masks 93A are formedalong side surfaces of the linear core members 91 in the memory cellarray region 12. In the memory cell array 2, the side wall masks 93Ahave a linear pattern and extend in the first direction.

The size (line width) of the side wall masks 93A in the memory cellarray 2 in the second direction is set, for example, smaller than alimit of processing executed by photolithography and is, for example,approximately the same as or smaller than the line width W1 of the coremembers 91. The adjacent pitch ptc3 of two side wall masks 93A adjacentin the second direction is the sum of, for example, the line width W3 ofthe side wall masks 93A and the line width of the core members 91.

As shown in FIGS. 15B and 15C, in the interconnect region 15, the sidewall masks 93A′ are formed on side surfaces of the core members 91′. Asdescribed above, since the core members 91′ in the interconnect region15 have the projecting portions 92 projecting in the second direction,the shape of the side wall masks 93′ in the interconnect region 15 iscurved due to the shape of the projecting portions 92. Hereinafter, inthe side wall masks 93A′ in the interconnect region 15, portions 94A,which are curved in response to the shape of the projecting portions 92,are particularly called curved portions 94A. The curved portions 94Ahave, for example, a concave (or U-like) plane shape.

In side wall masks 93A′ adjacent to each other in the second directionin the interconnect region 15, the pitch ptc4 of the portions other thanthe curved portions 94A is substantially the same as the sum of the linewidth W2 of the core members 91′ and the line width W4 of the side wallmasks 93A′.

The size (line width) W4 of the side wall masks 93A′ in the interconnectregion 15 in the second direction is substantially the same as, forexample, the line width W3 of the side wall masks 93A in the memory cellarray region 12. The side wall masks 93A′ of the curved portions 94Aalso have the line width W4.

However, the line width W4 of the side wall masks 93A′ may be differentfrom the line width W3 of the side wall masks 93A depending on theadjacent pitch ptc4 between the core members 91′. In other words, thesize of the line width W4 of the side wall masks 93A and the curvedportions 94A can be controlled by adjusting the adjacent pitch ptc4.

The curved portions 94A of the side wall masks 93A′ and the portions ofthe projecting portions 92 adjacent to the curved portions 94A have aninterval via which they are not in contact with each other. The intervalis set by adjusting the interval between the projecting portions 92 ofthe core members 91′ of FIG. 14B and the core members 91′ adjacent tothe projecting portions 92 when the projecting portions 92 are formed.

FIG. 16A shows a plane structure of the interconnect region 15 in aprocess of the manufacturing method of the resistance change memory asthe specific example of the embodiment. FIG. 16B shows a sectionalstructure along an H-H′ line of FIG. 16A and a sectional structure alongan I-I′ line of FIG. 16A. Note that, in the process, since the structureof the memory cell array region 12 is substantially the same as that inthe manufacturing process shown in FIGS. 15A, 15B, and 15C, illustrationof the structure will not be repeated here.

In the process shown in FIGS. 16A and 16B, the core members in thememory cell array region 12 and in the interconnect region 15 areselectively removed using, for example, wet etching, RIE, and the like.As a result, opening portions OP are formed which are surrounded by thecurved portions 94A of the side wall masks 93A′ as well as parts ofwhich have segmented portions in which the side wall masks 92, 93A′ aresegmented. Thereafter, in the interconnect region 15, resist masks 95Aare formed on the stacked bodies 101 using photolithography.

The resist masks 95A are formed to bridge one ends and the other ends ofthe side wall masks 93A′ segmented in the segmented portions of theopenings OP formed to the curved portions 94A in the first direction.The portions, which are surrounded by the curved portions 94A and theresist masks 95A, are made into cavities. The resist masks 95A areformed so as not to be in contact with the portions of the curvedportions 94A adjacent thereto in the second direction.

As shown in FIGS. 16A and 16B, ring-like mask patterns 99A are formed bythe resist masks 95A and the curved portions 94A of the side wall masks93A′. Further, the opening OP, which are surrounded by the ring-likemask patterns 99A, are made into cavities, and upper surfaces of thestacked bodies 101 are exposed via the openings OP.

The size X1 of the openings OP of the ring-like mask patterns 99A in thefirst direction depends on an interval between the two portions of thecurved portions 94A extending in the second direction. That is, the sizeX1 of the openings OP of the mask patterns 99A in the first direction isdetermined by the size of the projecting portions 92 of the core members91′ of FIG. 14B in the first direction.

The size Y2 of the openings OP of the ring-like mask patterns 99A in thesecond direction depends on the magnitude of the curved portions 94A inthe second direction, the positions where the resist masks 95A areformed to the curved portions 94A, and the magnitude (size) of theresist masks 95A.

Note that, in the memory cell array region 12, only the core members areremoved and the resist masks are not formed.

The conductive layer and the stacked bodies are processed using the sidewall masks 93A, 93A′, 94A and the resist masks 95A.

FIG. 17 shows a sectional structure after the conductive layer and thestacked bodies are processed using the side wall masks and the resistmasks. FIG. 17 shows sectional structures disposed side by side afterthe processing, the sectional structures corresponding to the F-F′ lineof FIG. 15A, a J-J′ line of FIG. 15A, the H-H′ line of FIG. 16A, and theI-I′ line of FIG. 16A.

In the memory cell array region 12, stacked bodies 100B and the controllines L2 which extend in the first direction are formed based on thelinear side wall mask extending in the first direction.

Further, the stacked bodies extending in the second direction on thecontrol lines L1 are processed based on the side wall mask extending inthe first direction and divided to the cell units CU1. However, in theprocess, the lower control lines L1 are not etched. The cell units CU1are disposed at the locations where the lower control lines L1 intersectthe upper control lines L2. When the memories operate, the control linesL1 or the control lines L2 are driven as the word lines, and theremaining control lines are driven as the bit lines.

As described above, the memory cell array M1, in which the cell unitsCU1 are two-dimensionally disposed, is formed in the memory cell arrayregion 12.

Simultaneously with the processing of the memory cell array region 12,the conductive layer in the interconnect region 15 is processed by theside wall masks 93A′ and the resist masks 95A shown in FIGS. 16A and16B.

With this operation, the interconnect 40A, which extends from the memorycell array region 12 to the interconnect region 15, is formed based on apredetermined interconnect layout and shape. For example, the controllines L2 in the memory cell array region 12 are not cut off from theinterconnect 40A in the interconnect region 15 and are configured ascontinuous conductive wires.

The ring-like contact portions 41A are formed to the interconnect 40A inthe interconnect region 15 by the ring-like mask patterns 99A composedof the resist masks 95A and the side wall masks 93A′ in the curvedportions 94A. The opening portion 49A of the contact portion 41A isformed in the ring portion 48.

The line width and the area of the ring portion 48A of the contactportion 41A are determined corresponding to the line widths of the sidewall masks 93A′ and the resist masks 95A. The magnitude of the openingportion 49 of the contact portion 41A is determined corresponding to thesizes of the projecting portions 92 of the core members 91′ in the firstand second directions, the size of the resist masks 95A, and thepositions where the resist masks 95A are formed to the curved portions94A of the side wall masks 93A′.

In the process shown in FIGS. 14A, 14B, and 14C, when the core members91′ are formed, the projecting portions disposed to the core members 91′are alternately projected toward adjacent core members side in two coremembers adjacent to each other in the second direction. Accordingly, thering-like contact portions 41A, which are processed based on the coremembers 91′ and the side wall masks 93A′, are disposed also alternatelytoward adjacent interconnects side in two interconnects. That is, alayout in the interconnect region 15 does not have a layout in which twocontact portions 41A face each other.

As described above, since the positions where the ring-like contactportions 41A are formed are alternately offset to adjacentinterconnects, even if the plane shape of the contact portion 41A isformed in the ring shape, an increase of the area occupied by theinterconnect region, which is caused by the formation of the contactportion 41A, is suppressed.

As shown in FIG. 17, the two memory cell arrays M1, M2 are processed inthe second direction at the same time. Simultaneously with theprocessing, the interconnects in the interconnect region 15 areprocessed at the same time. Thereafter, the side wall masks and theresist masks are removed. Further, in the interconnect region 15,components of the stacked bodies 100B remaining in the interconnectregion 15 are removed. Note that the same components as the stackedbodies 100B in the interconnect region 15 may not be removed and mayremain in the interconnect region 15 as dummy layers.

Thereafter, interlayer insulation films (not shown) are buried betweenthe cell units CU1 adjacent to each other in the second direction andbetween the stacked bodies 100B adjacent to each other in the seconddirection using, for example, coating and CVD. At the same time,interlayer insulation films are deposited also in the interconnectregion 15.

FIG. 18A shows a plane structure of the interconnect region 15 in aprocess of the manufacturing method of the resistance change memory asthe specific example of the embodiment. FIG. 18B shows a sectionalstructure along an H-H′ line of FIG. 18A and a sectional structure alonga K-K′ line of FIG. 18A. Further, FIG. 18B shows also a sectionalstructure of the memory cell array region 12 along the second directionin the process shown in FIG. 18A.

In the process shown in FIGS. 18A and 18B, a conductive layer and acomponent of the third memory cell array M3 from the substrate side aresequentially deposited on the components (stacked bodies) of the secondmemory cell array M2 by processes substantially the same as theprocesses shown in FIGS. 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, and 17.The stacked bodies for configuring the memory cell array M2 and stackedbodies 100C for configuring the memory cell array M3 are processed inthe first direction at the same time. The control lines L3 extending inthe second direction are formed simultaneously with the processing ofthe memory cell arrays M2, M3.

Ring-like contact portions are formed to the interconnects in theinterconnect region on the second direction side with respect to, forexample, the control lines L3 by the same processes as those shown inFIGS. 14A to 17.

After the cell unit CU2 that configures the second memory cell array M2is formed, an interlayer insulation film 82 is deposited in the memorycell array region 12 and in the interconnect region 15.

In the memory cell array region 12 and in the interconnect region 15, aconductive layer 59B for forming control lines extending in the firstdirection is deposited on the insulation film 82. Further, components100D′ of the fourth memory cell array M4 from the substrate side areformed on the conductive layer 59B.

As shown in FIGS. 18A and 18B, linear side wall masks 93B are formed inthe memory cell array region 12 and side wall masks 93B′ having curvedportions 94B are formed in the interconnect region 15 on the components100D′ by the same processes as those shown in FIGS. 14A, 14B, 14C, 15A,15B, 15C, 16A, and 16B. Further, resist masks 95B are formed on thestacked bodies 100D′ across openings of the curved portions 94B. Withsuch configuration, ring-like mask patterns 99B are formed above theinterconnect 51 and the conductive layer 59B. For example, the ring-likemask patterns 99B are formed at the positions where they are notoverlapped vertically on the ring-like contact portions 41A formed atinterconnect levels below the mask patterns 99B (in the thirddirection).

The portions surrounded by the curved portions 94B and the resist masks95B are configured as cavities having certain sizes in the first and thesecond directions. The size of cavities of the mask patterns 99B forforming the contact portions of an upper interconnect may or may nothave the same size as the opening portions 49 of the ring-like contactportions 41A of the lower interconnect 40A.

As shown in FIGS. 18A and 18B, the contact portion formed by thering-like mask patterns 99B is formed at an interconnect level above theinterconnect 40A.

As described above, the mask pattern is formed so that the ring-likecontact portions have an alternate layout in planes in interconnectsadjacent to each other in the second direction (or in the firstdirection) when viewed from the third direction as to also the contactportions disposed respectively to the interconnects at differentinterconnect levels. As a result, the area occupied by the interconnectregion 15 in which the ring-like contact portions are disposed can bereduced.

The stacked bodies for configuring the third memory cell array M3 andthe fourth memory cell array are formed in the memory cell array region12 using the side wall masks and the resist masks, and the interconnectshaving the ring-like contact portions are formed in the interconnectregion 15. Thereafter, in the interconnect region 15, the components ofthe cell units are removed, and interlayer insulation films aredeposited in the memory cell array region 12 and in the interconnectregion 15.

FIGS. 19A and 19B show a process of the manufacturing process of theresistance change memory as the specific example of the embodiment.FIGS. 19A and 19B show a sectional structure of the process of themanufacturing process for the interconnect region 15, and the sectionalstructure corresponds to cross sections along the H-H′ line and the K-K′line of FIG. 18A. Note that illustration of the manufacturing processfor the memory cell array region 12 will not be repeated here.

As shown in FIG. 19A, after the ring-like contact portions 41A, 41B areformed at two different interconnect levels, contact holes CHA, CHB areformed to bury contact electrodes 60A to the interconnects 40A, 40B atdifferent interconnect levels therein, respectively. The contact holesCHA, CHB are formed in the interlayer insulation films 81, 82, 83 byexecuting etching once. The contact holes CHA, CHB partially exposeupper surfaces of the ring-like contact portions 41A, 41B disposed tothe interconnects 40A, 40B, respectively, as well as expose uppersurfaces of the interconnect 50 and the interconnect 51 via the openingportions 49A, 49B of the contact portions 41A, 41B. As shown in FIG.19B, the contact electrodes 60A, 60B are buried in the contact holesCHA, CHB at the same time.

As described above, since the contact holes CHA, CHB are collectivelyprocessed (etched) to the interconnects at the interconnect levels, thenumber of processes for manufacturing the resistance change memory isreduced.

In a conventional contact electrode forming process, when one contactelectrode is formed to interconnects disposed below an interconnectlevel, the contact electrode 60A connected to lower and upperinterconnects is aligned to any one interconnect of the interconnects atinterconnect levels and cannot be directly aligned to the otherinterconnects. Accordingly, there is a possibility that the alignment ofthe contact electrode 60A to the interconnects which cannot be directlyaligned to the contact electrode 60A is offset. This may cause adeterioration of a manufacturing yield of the resistance change memory.To prevent the deterioration of the manufacturing yield, it is necessaryin a conventional resistance change memory to increase the size of theinterconnects and the size of contact portions disposed to theinterconnects or the size of contact holes to increase an alignmentmargin.

Further, the contact areas between the contact electrode and therespective interconnects are dispersed by the alignment offset. Inparticular, in the interconnects which cannot be directly aligned to thecontact electrode, since only a part of the contact electrode comes intocontact with (hooked to) parts of the interconnects (contact portions),the interconnects are greatly affected by the alignment offset.

As a result, there is a possibility that the contact resistances betweenthe contact electrode and the respective interconnects are dispersed andthus the electric characteristics of the interconnects are dispersed.

In the semiconductor device, for example, in the resistance changememory of the embodiment, the contact portions 41A, 41B formed to theinterconnects 40A, 40B have the ring-like plane shape.

An alignment between the contact electrodes 60A, 60B and theinterconnects 40A, 40B having the ring-like contact portions 41A, 41B isdetermined by the ring portions 48A and 48B of the contact portions 41A,41B.

An alignment of the contact electrodes 60A, 60B to the interconnectsbelow the interconnects 40A, 40B having the ring-like contact portions41B, 41B is determined by the sizes X1, X1′ in the first direction andthe sizes in the second direction of the opening portions (inside of thering portions) 49A, 49B of the ring-like contact portions 41A, 41B.

That is, the alignment between the upper interconnects 40A, 40B and thecontact electrodes 60A, 60B is set within the range of the areas of thering portions 48A, 48B, and an alignment between the lower interconnects50, 51 and the contact electrodes 60A, 60B is set within the range ofthe magnitudes of the opening portions 49A, 49B.

Therefore, when the contact portions 41A, 41B have the ring-like planeshape as in the resistance change memory as the specific example of theembodiment, it is sufficient to determine the alignment of the contactelectrodes 60A, 60B (the positions where the contact holes are formed)only in consideration of an alignment offset between the contactportions 41A, 41B and the interconnects below the contact portions 41A,41B.

Accordingly, when the ring-like contact portions 41A, 41B are formed tothe interconnects 40A, 40B as in the resistance change memory of theexample, a restriction to an alignment for forming the contact electrode60A, 60B is relaxed in the contact electrodes 60A, 60B which arecommonly connected to the interconnects 40A, 40B, 50, 51 acrossinterconnect levels.

Further, when the sizes and the areas of the ring portions 48A, 48B ofthe contact portions 41A, 41B are designed in consideration of analignment offset between the contact electrodes 60A, 60B and the contactportions, a dispersion of the contact areas A-xy, A′-xy between thecontact electrodes 60A, 60B and the ring-like contact portions 41A, 41Bcan be suppressed in the respective interconnects 40A, 40B having thecontact portions 41A, 41B.

Further, since the contact electrodes 60A, 60B are in contact with theupper surfaces of the ring-like contact portions 41A, 41B, even when thecontact electrodes 60A, 60B and the contact portions 41A, 41B cause analignment offset in any of the first direction and the second directionor in both the first and second directions, the dispersion of thecontact areas A-xy, A′-xy between the contact electrodes 60A, 60B andthe ring-like contact portions 41A, 41B can be suppressed.

As a comparative example, a case, in which the resist masks 95A are notformed and the ring-like contact portions are partially segmented inFIG. 16A, will be examined. In the comparative example, when the contactelectrodes 60A, 60B and the contact portions 41A, 41B cause an alignmentoffset in the second direction, the contact areas between the contactelectrodes 60A, 60B and the contact portions 41A, 41B are changed ascompared with a case in which they do not cause the alignment offset. Asa result, the contact resistances between the contact electrodes 60A,60B and the interconnects 40A, 40B are changed.

In contrast, since the contact portions 41, 41B have the ring-like planeshape, even when the contact electrodes 60A, 60B and the contactportions 41A, 41B cause an alignment offset in any of the first andsecond directions or in both the first and second directions, thecontact areas A-xy, A′-xy between the contact electrodes 60A, 60B andthe ring-like contact portions 41A, 41B remain constant. As a result, achange of the contact resistances between the contact electrodes 60A,60B and the interconnects 40A, 40B can be prevented.

A dispersion of the contact areas B-xy, B-xy′ between the contactelectrodes 60A, 60B and the interconnects 50, 51 can be suppressed alsofor the lower interconnects 50, 51 similarly to the upper interconnects40A, 40B by adjusting the sizes and the areas of the opening portions49A, 49B of the contact portions 41A, 41B.

In addition to that mentioned above, the contact areas B-xy, B′-xybetween the lower interconnects 50, 51 and the contact electrodes 60A,60B can be set by controlling the magnitudes of the opening portions(inside of the ring portions 48A, 48B) 49A, 49B of the contact portions41A, 41B in consideration of the contact areas A-xy, A′-xy between theupper interconnects 40A, 40B and the contact electrodes 60A, 60B.

Therefore, a dispersion of the contact resistance of the interconnectsdue to a dispersion of the contact areas can be suppressed.

Note that the sizes of the ring portions 48A, 48B and the openingportions 49A, 49B of the contact portions 41A, 41B can be controlled bythe magnitude of the projecting portions of the core members which areformed by the processes shown in FIGS. 14A, 14B, 14C, 15A, 15B, 15C,16A, 16B, 17, 18A, and 18B, the size of the side wall masks in theinterconnect region 15, the size of the resist masks, and the positionswhere the resist masks are formed to the curved portions.

Thereafter, substantially the same processes as those shown in FIGS. 14Ato FIG. 18B are repeatedly executed until the number of the memory cellarrays and the interconnects in the memory cell array region 12 reachesa predetermined stack number.

Note that although the manufacturing process for the interconnect region15 adjacent to the memory cell array region 12 in the first directionhas been described here, interconnects having ring-like contact portionsand contact electrodes connected to the interconnects at respectiveinterconnect levels can be formed in also an interconnect regionadjacent to the memory cell array region 12 in the second direction bysubstantially the same processes as those described using FIGS. 14A to18B except that control lines and the interconnects have differentinterconnect levels.

Although the masks for forming the ring-like contact portions are formedby combining the side wall masks and the resist masks here, the masksfor forming the ring-like contact portions may be formed of only theresist masks.

The resistance change memory as the specific example of the embodimentas shown in FIGS. 8, 9, 10, 11, 12, and 13 is completed by the processesdescribed above.

As described using FIGS. 8 to 13, the interconnects 40A, 40B in theinterconnect region 15 include the ring-like contact portions 41A, 41B.The contact electrodes 60A, 60B are electrically connected to the upperinterconnects 40A, 40B by coming into contact with the ring portions48A, 48B of the contact portions 41A, 41B. Together with suchconfiguration, the contact electrodes 60A, 60B are electricallyconnected to the lower interconnects 50, 51 via the opening portions49A, 49B of the ring-like contact portions 41A, 41B.

With such configuration, in a semiconductor device such as theresistance change memory in which one contact electrode 60 is disposedacross the stacked interconnects 40A, 40B, 50, 51, an alignment of thecontact electrodes 60A, 60B to the lower interconnects 50, 51 isdetermined by the sizes and the positions inside (the opening portions49A, 49B) of the ring portions 48A, 48B of the contact portions 41A,41B.

Accordingly, a restriction of an alignment between the respectiveinterconnects 40A, 40B, 50, 51 and the contact electrodes 60A, 60B, forexample, a restriction of an alignment between the interconnects and thecontact electrodes from a process viewpoint of, for example, an aspectratio between the interconnects, a change of the size of theinterconnects due to a proximity effect, and the like is relaxed.

Therefore, according to the embodiment, a margin can be secured for analignment offset of the contact electrodes connected between theinterconnects having different interconnect levels.

The contact areas between the upper interconnects 40A, 40B having thering-like contact portions 41A, 41B and the contact electrodes 60A, 60Bare determined by the magnitudes (line widths) of the ring portions 48A,48B of the contact portions 41A, 41B. The contact areas between thelower interconnects 50, 51 and the contact electrodes 60A, 60B aredetermined by the magnitudes of the opening portions 49A, 49B.

Accordingly, since the contact areas between the respectiveinterconnects 40A, 40B, 50, 51 and the contact electrodes 60A, 60B canbe made substantially the same by adjusting (controlling) the sizes ofthe ring portions 48A, 48B in the contact portions 41A, 41B and thesizes of the opening portions 49A, 49B, a dispersion of the contactresistances can be suppressed. Thus, according to the embodiment, adispersion of the electric characteristics generated by the respectiveinterconnects can be suppressed.

When the line widths of the ring portions 48A, 48B are increased, sincethe sizes Xce, Yce of the upper electrode portion 61 can be increased,the contact area between the upper electrode portion 61 of the contactelectrode 60 and the contact portion 41 can be increased. As a result,the contact resistances between the upper interconnects 40A, 40B and thecontact electrodes 60A, 60B can be reduced.

Further, the areas of the opening portions 49A, 49B are increased. Thecontact areas between the lower interconnects 50, 51 and the contactelectrodes 60A, 60B can be adjusted (controlled) by the sizes of theopening portion portions 49A, 49B. Therefore, since the contact areasbetween the lower interconnects 50, 51 and the contact electrodes 60A,60B can be increased by increasing the areas of the opening 49A, 49B,the contact resistances between the contact electrodes 60A, 60B and thelower interconnect layers 50, 51 can be reduced.

As described above, in the embodiment, the contact resistances betweenthe interconnects 50, 51 and the contact electrodes 60A, 60B can bereduced by adjusting the areas of the ring portions 48A, 48B and theopening portions 49A and 49B. Further, the magnitude of the contactareas between the lower interconnects 50, 51 and the contact electrodes60A, 60B can be the same as magnitude of the contact areas as thosebetween the upper interconnects 40A, 40B and the contact electrodes 60A,60B by adjusting the line widths of the ring portions 48A, 48B and theareas of the opening portions 49A and 49B. As a result, since themagnitudes of the contact resistances between the upper interconnects40A, 40B and the contact electrodes 60A, 60B can be made to be the sameas those of the contact resistances between the lower interconnects 50,51 and the contact electrodes 60A, 60B, the dispersion of the contactresistances generated to the respective interconnects can be reduced.

As described above, the manufacturing method of the semiconductor device(for example, the resistance change memory) according to the embodimentcan manufacture the semiconductor device in which occurrence of thealignment offset of the interconnects and the dispersion of the electriccharacteristics of the interconnects are suppressed. As a result, themanufacturing method of the semiconductor device according to theembodiment can provide the semiconductor in which the contact electrodescan be stably connected to the interconnects.

(3) Modification

A modification of the semiconductor device (for example, the resistancechange memory) according to the embodiment will be described using FIGS.20, 21A, 21B, 22A, 22B, and 23.

As described using FIGS. 16A and 18A, a mask pattern whose plane shapeis formed in a ring-like mask pattern is formed by combining a curvedportion of a side wall mask with a resist mask. A contact portion havinga ring-like plane shape is formed to an interconnect by processing aconductive layer based on the ring-like mask pattern.

When one mask pattern is formed by combining the side wall mask and theresist mask, the plane shape of the ring-like contact portion is changedin response to a position where the resist mask is formed to the curvedportion of the side wall mask.

FIG. 20 is a plan view showing a layout of the curved portion 94 of theside wall mask and the resist mask 95. The size DX1 of the inside (anopening portion 49X) of the portion of the side wall mask surrounded bythe curved portion 94 in the x-direction is set by the size of aprojecting portion (refer to FIG. 14B) of a core member for forming theside wall mask in the x-direction (first direction of FIG. 14B), and thesize DY1 of the inside (the opening portion 49X) of the portionsurrounded by the curved portion 94 in the y-direction is set by thesize of the projecting portion of the core member in the y-direction(second direction of FIG. 14B).

To form the ring-like mask pattern, the resist mask 95 is formed from anend to the other end of the side wall mask 93 segmented by the curvedportion 94 to bridge the opening portion 49X formed by the curvedportion 94 in the x-direction. Accordingly, the size DL1 of the resistmask 95 in the x-direction is set equal to or larger than the size DX1of the opening portion 49X in the x-direction.

However, to form the ring-like mask pattern, it is necessary to adjustthe size DW1 of the resist mask 95 in the y-direction and a positionwhere the resist mask 95 is formed on the curved portion 94 so that theresist mask 95 does not entirely cover the opening portion 49X.

The plane shape of the ring-like contact portion is changed in responseto the size DW1 of the resist mask 95 in the y-direction and theposition, where the resist mask is formed, to the curved portion 95.

FIGS. 21A and 21B show plane structures of ring-like contact portions41V, 41X disposed to interconnects in the modification of thesemiconductor device (for example, the resistance change memory) of theembodiment, respectively.

When, for example, the size DW1 of the resist mask is larger than thesize (line width) MW of the side wall mask 93 in the y-direction in FIG.20, the ring-like contact portion 41V includes a portion (first portion)48 curved from an interconnect and a portion (second portion) 47Bprojecting (swelling) in an opposite direction of the curved portion 48as shown in FIG. 21A.

Even when the position where the resist mask 95 of FIG. 20 is formed isoffset to a side opposite to the side to which the curved portion (ringportion) is curved on the side wall mask, a projecting portion 47A isalso formed to the contact portion 41V as shown in FIG. 21A.

The line width (size in the y-direction) RWa of the second portion 47Ais thicker than, for example, the line width RW of the first portion 48.Note that the line width RWa of the second portion 47A is thicker than,for example, the line width of an interconnect 40. The line width RW ofthe ring portion 48 is equal or thicker than, for example, the linewidth of the interconnect 40. Further, the size dRW1 of the projectingportion in a direction (y-direction) intersecting in the extendingdirection (x-direction) of the interconnect depends on the projectingmagnitude of the resist mask 95 projecting from the interconnect 40 inthe y-direction in FIG. 20. When, for example, the width of theinterconnect 40 (the line width MW of the side wall mask 93) is thinnerthan the line width RW of the first portion 48, an alignment margin isreduced when a position where a contact hole is formed is offset to aside opposite to the side to which the mask is curved. To cope with theproblem, the alignment margin can be increased when the position wherethe contact hole is formed is offset to the side opposite to the side towhich the mask is curved by making the size DW1 of the resist mask 95thicker than the line width MW of the side wall mask 93. As a result, acontact electrode can be stably connected to the interconnects.

The size dLA1 of the projecting portion in an interconnect extendingdirection (x-direction) depends on the size DL1 of the resist mask 95 ofFIG. 20 in the x-direction. The size of the projecting portion (secondportion) 47A in the x-direction is larger than the size of the inside(opening portion 49) of the ring portion 48 in the x-direction. However,the size dLA1 of the projecting portion in the interconnect extendingdirection (x-direction) may be smaller or larger than the size RWx ofthe outside of the ring portion 48 in the x-direction.

In contrast, when the size DW1 of the resist mask 95 of FIG. 20 in they-direction is smaller than the size (line width of a formedinterconnect) MW of the side wall mask 93 in the y-direction or when theposition, where the resist mask 95 of FIG. 20 is formed, is offset to aside to which the curved portion (ring portion) 94 projects, the contactportion 41X has a shape in which a portion thereof facing the curvedportion of the ring portion 48 is recessed to the side to which the ringportion 48 is curved. Further, the size dRW2 of the recess in adirection (y-direction) intersecting in the interconnect extendingdirection depends on the magnitude of the resist mask 95 recessed fromthe interconnect 40 (side wall mask) in FIG. 20 in the y-direction.

Although the example described above shows a structure in which the ringportion and the opening portion of the contact portion disposed to theinterconnect have a square plane shape, the plane shape of the contactportion may be deformed in response to a shape of the mask (core member)and an etching condition.

FIGS. 22A and 22B show plane structures of the ring-like contactportions 41Y, 41Z disposed to the interconnects in the modification ofthe semiconductor device (for example, the resistance change memory) ofthe embodiment, respectively.

As shown in, for example, FIG. 22A, the plane shape of a ring portion48Y of a contact portion 41Y may have a pattern including a curved linesuch as an oval shape and a circular shape. In the case, the plane shapeof an opening portion 49Y may also have the oval shape and the circularshape.

Further, as shown in FIG. 22B, the plane shape of a ring portion 48Z ofa contact portion 41Z may have a square shape with no corners, and thering portion 48Z may have a polygonal plane shape. Likewise, an openingportion 49Z may also have a polygonal shape without corners. Further,the ring portion 48Z and the opening portion 49Z may have a square shapewithout corners.

FIG. 23 shows sectional structures of ring-like contact portions 71X,71Y and a contact electrode 60Z disposed to interconnects 40X, 40Y inthe modification of the semiconductor device (for example, theresistance change memory) of the embodiment.

In the example described above, a case, in which one contact electrodeis formed across two stacked interconnects via a ring-like contactportion disposed to the interconnects, will be exemplified. However, asshown in FIG. 23, the contact electrode 60Z may be formed across atleast three interconnects 40X, 40Y, 40Z via the ring-like contactportions 71X, 71Y.

Also in the case, the contact areas between the respective interconnects40X, 40Y, 40Z and the contact electrode 60Z can be made substantiallythe same by adjusting (controlling) the size D1 of contact holes formedto interlayer insulation films (not shown), the sizes RW1, RW2 of ringportions 78X, 78Y of contact portions 70X, 70Y, and the sizes D2, D3 ofopening portions 79X, 79Y of the contact portions 70X, 70Y.

As shown in FIG. 23, when the one contact electrode 60Z passes throughthe opening portions 79X, 79Y of the contact portions 71X, 71Y, the sizeD2 of the opening portion 79X of the contact portion 71X positioned toan upper layer is larger than the size D3 of the opening portion 79Y ofthe contact portion 71Y of a lower layer.

Note that the contact portion 71Y between the contact portion 71Xconnected to the interconnect 40X and the interconnect 40Z on asubstrate 11 may be an intermediate layer which is not connected to anyinterconnect.

Further, as shown in FIG. 23, respective portions 61, 62, 63 of thecontact electrode 60Z may have a taper (trapezoidal) sectional shapewith an upper surface side size larger than a bottom surface side sizeaccording to the intervals H1, H2, H3 of the stacked interconnects 40X,40Y, 40Z. The intervals H1, H2, H3 correspond to, for example, the filmthickness of the interlayer insulation films (not shown) interposedbetween the interconnects.

The same effect as those of the basic example and the applied exampledescribed above can also be obtained even in the modification of thesemiconductor device of the embodiment (for example, the resistancechange memory) shown in FIGS. 21A, 21B, 22A, 22B, and 23.

Note that all the contact portions of the semiconductor device (forexample, the resistance change memory) need not have the same planeshape as long as the plane shape of the contact portions have thering-like plane shape, and the plane shape of the contact portions maybe a square shape in certain interconnects and may be an oval shape inthe other interconnects.

As described above, the contact electrodes can be stably connected tothe interconnects also in the modification of the semiconductor deviceof the embodiment.

[Other]

The semiconductor device according to the embodiment can be applied toresistance change memories such as ReRAM and PCRAM.

Although the resistance change memory having the cross point type memorycell array has been described in the embodiment, the embodiment is notlimited thereto. The ring-like contact portions described in theembodiment can be applied to, for example, interconnects of a flashmemory (BiCS memory) formed by, for example, a BiCS (Bit Cost Scalable)technology. Further, it is needless to say that the embodiment can beapplied to a semiconductor integrated circuit such as a logic circuit inaddition to the memories described above.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

1. A semiconductor device comprising: a substrate; and an interconnectregion on the substrate, the interconnect region including a firstinterconnect having a first contact portion whose plane shape is aring-like plane shape, a second interconnect disposed below the firstinterconnect, and a contact electrode passing through the ling-likeportion of the first contact portion and electrically connecting thefirst interconnect and the second interconnect.
 2. The semiconductordevice according to claim 1, wherein the interconnect region furtherincludes a third interconnect having a second contact portion whoseplane shape is a ring-like plane shape, and is disposed at a positionadjacent to the first interconnect in a plane, the first contact portionprojects to the third interconnect side with respect to the surface ofthe substrate in a horizontal direction, and the second contact portionprojects to the first interconnect side with respect to the surface ofthe substrate in the horizontal direction.
 3. The semiconductor deviceaccording to claim 2, wherein the first contact portion and the secondcontact portion project in an alternate direction.
 4. The semiconductordevice according to claim 1, wherein the interconnect region furtherincludes a fourth interconnect having a third contact electrode whoseplane shape is a ring-like plane shape, and is disposed at aninterconnect level different from the first interconnect, and the thirdcontact portion is disposed at a position which does not overlap thefirst contact portion in a vertical direction with respect to thesurface of the substrate.
 5. The semiconductor device according to claim1, wherein the first contact portion includes: a first portionprojecting from the first interconnect in a direction intersecting theextending direction of the first interconnect; and a second portionprojecting to a side opposite to the side to which the first portionprojects.
 6. The semiconductor device according to claim 5, wherein theline width of the second portion is wider than the line width of thefirst portion.
 7. The semiconductor device according to claim 1, whereinthe contact electrode includes: a first electrode portion on the uppersurface of the first contact portion; and a second electrode portionpassing through a ring-like portion of the first contact portion and incontact with the second interconnect, and the size of the firstelectrode portion in the horizontal direction with respect to thesurface of the substrate is larger than the size of the second electrodein the horizontal direction with respect to the surface of thesubstrate.
 8. The semiconductor device according to claim 7, wherein thesecond electrode portion is in contact with a side surface of an openingportion of the contact portion and with the upper surface of the secondinterconnect.
 9. The semiconductor device according to claim 1, furthercomprising: a cross point type memory cell on the substrate adjacent tothe interconnect region, the cross point type memory cell including afirst control line extending in a first direction, a second control lineextending in a second direction intersecting the first direction, and acell unit disposed at a position where the first control line intersectsthe second control line and including a memory device for storing datain response to a reversible change of a resistance state.
 10. Thesemiconductor device according to claim 9, wherein the first controlline is disposed at the same interconnect level as the firstinterconnect.
 11. The semiconductor device according to claim 9, whereinthe first interconnect is connected to the first control line.
 12. Asemiconductor device comprising: a substrate; an interconnect region onthe substrate, the interconnect region including a first interconnecthaving a first contact portion whose plane shape is a ring-like planeshape, a second interconnect disposed below the first interconnect, anda contact electrode passing through the ling-like portion of the contactportion and electrically connecting the first interconnect and thesecond interconnect; and a memory array region on the substrate adjacentto the interconnect region, the memory array region including a firstcontrol line extending in a first direction, a second control lineextending in a second direction intersecting the first direction, athird control line extending in the first direction and disposed at aninterconnect level different from the first control line, and cell unitshaving a memory device connected to the first and second control linesand connected to the second and third control lines, respectively. 13.The semiconductor device according to claim 12, wherein the interconnectregion further includes a third interconnect having a second contactportion whose plane shape is a ring-like plane shape and disposed at thesame interconnect level as the third control line, and the secondcontact portion is disposed at a position which does not overlap thefirst contact portion in a vertical direction with respect to thesurface of the substrate.
 14. The semiconductor device according toclaim 12, wherein the interconnect region further includes a forthinterconnect having a third contact portion whose plane shape is aring-like plane shape and disposed at a position adjacent to the firstinterconnect in a plane, the first contact portion projects to thefourth interconnect side in a horizontal direction with respect to thesurface of the substrate, and the third contact portion projects to thefirst interconnect side in the horizontal direction with respect to thesurface of the substrate.
 15. The semiconductor device according toclaim 14, wherein the first contact portion and the second contactportion project in an alternate direction.
 16. The semiconductor deviceaccording to claim 12, wherein the first contact portion includes: afirst portion projecting from the first interconnect in a directionintersecting the extending direction of the first interconnect; and asecond portion projecting to a side opposite to the side to which thefirst portion projects.
 17. The semiconductor device according to claim16, wherein the line width of the second portion is wider than the linewidth of the first portion.
 18. The semiconductor device according toclaim 12, wherein the contact electrode includes: a first electrodeportion on the upper surface of the first contact portion; and a secondelectrode portion passing through the ring-like portion of the firstcontact portion and in contact with the second interconnect, and thesize of the first electrode portion in the horizontal direction withrespect to the surface of the substrate is larger than the size of thesecond electrode portion on the surface of the substrate.
 19. Thesemiconductor device according to claim 12, wherein the first controlline is disposed at the same interconnect level as the firstinterconnect, and the second control line is disposed at the sameinterconnect level as the second interconnect.
 20. The semiconductordevice according to claim 12, wherein the first interconnect isconnected to the first control line, and the second interconnect isconnected to the second control line.